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september 10 , 2012 | final datasheet 1 ir355 8 4 5 a integrated powirs tage ? features ? peak efficiency up to 9 4. 0 % at 1.2v ? integrated driver, control mosfet, synchronous mosfet and schottky diode ? input voltage (vin) operating range of 4.5v to 15 v ? separate lvcc and h v cc from 4.5v to 13.2v to optimize converter efficiency ? output curr ent capability of 45 a dc ? switching frequency up to 1.0mhz ? programmable thermal flag threshold from 70c to 150c ? 5v vcc with under voltage lockout ? low quiescent current ? enable control ? selectable regular 3.3v tri - state pwm logic or ir active tri - level (atl) pwm logic ? pcb footprint c ompatible with most ir3551 pins ? efficient dual sided cooling ? small 5 mm x 6 mm x 0.9mm pqfn package ? lead free rohs compliant package applications ? voltage regulators for cpus, gpus, an d ddr memory arrays ? high current , low profile d c - dc converters basic application figure 1: ir 3558 basic application circuit description the ir 3558 int egrated powirs tage ? is a synchronous buck gate dr iver co - packed with a control mosfet and a synchronous mosfet with integrated schottky diode . it is optimized internally for pcb layout, heat transfer and driver/mosfet timing. custom designed gate driver and mosfet combination enables higher efficiency at lower output voltages required by cutting edge cpu , gpu and ddr memory designs. up to 1.0mhz sw itching frequency enables fast transient response, allowing miniaturization of output inductors as well as input and output capacitors while maintaining high efficiency. the ir 3558 s sup erior efficiency enables smallest size and lower solution cost. the ir 3558 pcb footprint is compati ble with most pins of the ir355 1 (5 0a) . the IR3558 provides two selectab le pwm logic modes, the 3.3v tri - state pwm logic or international rectifiers active tri - level tm (atl) pwm logic. the atl pwm logic eliminates a dedicated body - braking? pin and improves the transient response of the converter during load release. the IR3558 provides a thermal flag output with programmable threshold from 70c to 150c, which makes it possible to adjust the thermal protection threshold based on the pcb layout and thermal distribution. the ir 3558 is optimized specifically for cpu core power delivery in server applications. the ability to meet the stringent requirements of the server market also makes the ir 3558 ideally suited to powering gpu an d ddr memory designs and other high current applications . figure 2: typical ir 3558 efficiency & power loss (see note 2 o n page 7 ) sw vin pgnd vcc vcc boost vin vout otset 5 v lgnd pwm pwm enable en 4 . 5 v to 15 v ir 3558 ot # ot # cs + cs - hvcc lvcc mode pvcc 4 . 5 v to 13 . 2 v 75 77 79 81 83 85 87 89 91 93 95 0 5 10 15 20 25 30 35 40 45 output current (a) efficiency (%) 0 2 4 6 8 10 12 14 16 18 20 power loss (w)
september 10 , 2012 | final datasheet 2 ir355 8 4 5 a integrated powirs tage ? pinout diagram figure 3: ir 3558 pin diagram, top view ordering i nformation package tape & reel qty part number pqfn, 28 lead 5 mm x 6mm 4 000 ir 3558 mtrpbf typical application diagram figure 4 : application circuit sw pwm vin pgnd gate drivers and over temperat - ure detection mode vcc ot # pvcc vcc boost vin vout pwm lvcc ot # enable en otset otset lgnd ir 3558 4 . 5 v to 5 . 5 v 4 . 5 v to 15 v c 2 10 uf x 2 c 5 0 . 22 uf c 3 0 . 1 uf r 1 10 k c 6 0 . 22 uf r 2 2 . 49 k l 1 150 nh c 8 470 uf 1 16 - 19 20 21 22 23 26 25 2 24 14 , 15 6 - 13 c 1 0 . 1 uf pgnd 4 , 27 c 7 22 uf mode hvcc 3 4 . 5 v to 13 . 2 v cs + cs - c 4 1 uf
september 10 , 2012 | final datasheet 3 ir355 8 4 5 a integrated powirs tage ? functional block dia gram figure 5 : ir 3558 functional block diagram ot # pwm 6 7 8 9 10 11 12 13 16 17 18 19 vin vin vin vin sw sw sw sw sw sw sw sw 27 14 15 pgnd pgnd pgnd 20 boost power - on reset ( por ) , pwm mode , reference , and dead - time control 22 otset 26 lvcc 1 en 23 5 28 gatel gatel driver driver 21 24 lgnd 25 mode thermal detection vcc 4 pgnd ir 3558 3 hvcc 2 vcc
september 10 , 2012 | final datasheet 4 ir355 8 4 5 a integrated powirs tage ? pin descriptions pin # pin name pin description 1 vcc bias voltage for control logic. connect vcc to a 5 v supply. connect a minimum 0. 1uf cap acitor between vcc and l gnd . 2 lvcc s upply voltage for the low - side driver. connect lvcc to a 4.5v to 13.2v supply. connect a minimum 0.1uf cap acitor between l vcc and pgnd (pin 4) . 3 hvcc s upply voltage for the high - side driver. connect h vcc to a 4.5v to 13.2v supply. connect a minimum 0.1uf cap acitor between hvcc and pgnd (pin 4) . 4 , 14, 15, 27 pgnd power ground of low - side mosfet dri ver and the synchronous mosfet . 5, 28 gatel low - side mosfet driver pin s that can be connected to a test point in order to observe the waveform. 6 C 1 3 sw switch node of synchronous buck converter. 16 C 19 vin high current input voltage connection. recommended operating range is 4.5v to 15v. connect at least two 10uf 1206 ceramic capacitors and a 0.1uf 0402 ceramic capacitor. place the capacitors as close as possib le to vin pins and pgnd pins (14 - 15 ). the 0.1uf 0402 capacitor should be on the same s ide of the pcb as the IR3558. 20 boost bootstrap capacitor connection. the bootstrap capacitor provides the charge to turn on the control mosfet. connect a minimum 0.22f capacitor from boost to sw pin. place the capacitor as close to boost pin as possibl e and minimize the parasitic inductance of the connection from the capacitor to sw pin. a 1 to 4 series resistor may be added to slow down the sw rising and limit the surge current into the bootstrap capacitor on start - up. 21 ot # open drain output of t he phase fault circuits. connect to an external pull - up resistor. outpu t is low when an over temperature condition inside the device is detected. 22 pwm pwm control input . connect this pin to the pwm output of a controller that outputs either a 3.3v tri - state pwm signal or a 1.8v i nternational r ectifiers a ctive t ri - l evel pwm signal . 23 en enable control . 3.3v logic level input. pulling this pin high to enable the device and grounding it to shut down both mosfets and enter low quiescent mode. 24 l gnd signal ground. driver control logic, analog circuits and ic substrate are referenced to this pin. 25 mode pwm mode selection. grounding this pin to select the regular 3.3v tri - state pwm logic or connecting it to vcc to select i nternational r ectifiers a c tive t ri - l evel pwm logic. 26 otset over temperature set . the default is 150c when this pin is floated. a resistor from this pin to ground programs the over temperature threshold from 70c to 150c. see over temperature threshold set resistor r otset sec tion for the resistor selection details.
september 10 , 2012 | final datasheet 5 ir355 8 4 5 a integrated powirs tage ? absolute maximum rat ings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or an y other conditions beyond those indicated in the operational sections of the specifications are not implied. pin number pin name v max v min i s ource i sink 1 vcc 6.5 v - 0.3v na 10ma 2 lvcc 15v - 0.3v na 1a for 100ns, 100ma dc 3 hvcc 15v - 0.3v na 1a for 100ns , 100ma dc 4, 27 pgnd 0.3 v - 0.3v 15ma 15ma 5, 28 gatel lvcc + 0.3v - 3v for 20ns, - 0.3v dc 1 a for 100ns, 200ma dc 1 a for 100ns, 200ma dc 6 - 13 sw 2 2 5v - 5v for 20ns, - 0.3v dc 5 5a rms 25 a rms 14, 15 pgnd na na 25 a rms 55 a rms 16 - 19 vin 2 25 v - 0.3v 5a rm s 20a rms 20 boost 1 35 v - 0.3v 1 a for 100ns, 100ma dc 5a for 100ns, 100ma dc 21 ot# vcc + 0.3v - 0.3v 1 ma 20 ma 22 pwm vcc + 0.3v - 0.3v 1ma 1 ma 23 en vcc + 0.3v - 0.3v 1ma 1ma 24 l gnd 0.3v - 0.3v 10ma na 25 mode vcc + 0.3v - 0.3v 1ma 1ma 26 otset vcc + 0 .3v - 0.3v 1ma 1ma note: 1. maximum boost C sw = 15 v . 2 . maximum vin C sw = 25v . 3. all the m aximum voltage ratings are referenced to pgnd (pins 14 and 15 ) . thermal information thermal resistance , junction to top ( jc _top ) 18.2 c/w thermal resis tance , junction to pcb (pin 15 ) ( j b ) 2.6 c/w thermal resistance ( ja ) 1 20.8 c/w maximum operating junction temperature - 4 0 to 1 50 c maximum storage temperature range - 65c to 150c esd rating hbm class 1a jedec standard msl rating 3 reflow temp era ture 26 0c note : 1. thermal resistance ( ja ) is measured with the component mounted on a high effective thermal conductivity test board in free air . refer to international rectifier application note an - 994 for details .
september 10 , 2012 | final datasheet 6 ir355 8 4 5 a integrated powirs tage ? electrical specifica tions the el ectrical characteristics involve the spread of values guaranteed within the recommended operating conditions. typical values represent the median values, which are related to 25c. recommended operatin g conditions for rel iable operation with margin parame ter symbol min max unit recommended vin range vin 4.5 15 v recommended vcc range vcc 4.5 5.5 v recommended lvcc range lvcc 4.5 13.2 v recommended hvcc range hvcc 4.5 13.2 v recommended switching frequency ? sw 200 1000 khz recommended operating juncti on temperature t j - 40 125 c e lectrical characteri stics parameter symbol conditions min typ max unit efficiency powirstage peak efficiency note 2, figure 2 9 4.0 % note 3, figure 8 93.0 % pwm tri - state mode (figure 6 ) pwm input high threshol d v pwm_high pwm tri - state to high 2. 0 2.5 3.0 v pwm input low threshold v pwm_low pwm tri - state to low 0. 7 0.8 0.9 v pwm tri - state float voltage v pwm_tri pwm floating 0.85 1.6 0 2.55 v hysteresis v pwm_hys active to tri - state or tri - state to act ive, note 1 200 mv tri - state hold off time t pwm_hold note 1 80 ns pwm input impedance r pwm_sink 3.00 3.75 4.50 k minimum pulse width t pwm_min note 1 40 60 n s pwm active tri - level (atl) mode (figure 7 ) pwm input h igh threshold v atl_high 0.8 1.0 1.2 v pwm input h igh threshold v atl_low 0.65 0.8 0.95 v pwm tri - level high voltage v atl_tri_high 2.1 2.5 2.9 v pwm tri - level low voltage v atl_tri_low 2.00 2.3 0 2.42 v pwm input current low v pwm = 0v - 1.0 - 1.5 ma pwm input current high v pwm = 1.8v - 1.0 - 1.5 ma enable input C en input voltage h igh v n_ h 2.0 v input voltage l ow v en _l 0.8 v input c urrent i e n v(en ) = 5.5v 0 .1 1 a
september 10 , 2012 | final datasheet 7 ir355 8 4 5 a integrated powirs tage ? parameter symbol conditions min typ max unit thermal warning - otset input and ot# output over temperature high threshold ot r otset = open, note 1 150 c programmable over temperature high threshold ot r otset = 100k, note 1 125 c over temperature hysteresis ot hys note 1 - 2 0 c ot# sink current 1.0 1.5 ma ot# output low voltage 1.5ma 0. 4 1. 0 v bootstrap diode forward voltage bd fv i(boost) = 30ma, l vcc = 6.8v 0.65 0.80 0.95 mv vcc under v oltage lockout start threshold v vcc_start 3.5 3.8 4.1 v stop threshold v vcc_stop 3.2 3.5 3.8 v hysteresis v vcc_hys 0.15 0.3 0 0.45 v general vcc supply quiescent cu rrent i vcc v( vcc ) = 5 v, v(en) =0v 1. 5 2.5 ma vcc supply current i vcc _sw v( vcc) = 5 v, v(en) =5v 2. 7 3.5 ma lvcc supply quiescent current i lv cc v(lvcc) = 5 v, v(en) =0v 15 25 ua v(lvcc) = 7 v, v(en) =0v 20 30 ua lvcc supply current i lv cc _sw v (lvcc) = 5 v , v(en) =5 v , fsw=400khz 10 20 ma v (lvcc) = 7 v , v(en) =5 v , fsw=400k hz 15 25 ma hvcc supply quiescent current i boost v(hvcc) = 5v, v(en) =0v 15 25 u a v(hvcc) = 7 v, v(en) =0v 20 30 ua hvcc supply current i boost _sw v(hvcc) =5v, v(en) =5v , fsw=400khz 5 10 ma v(hvcc) =7v, v(en) =5v , fsw=400khz 6.5 15 ma vin s upply leakage current i vin vin = 20v, 125 c , v(pwm) = tri - state 1 a notes 1. guaranteed by design but not tested in production 2. v in =12v, v out =1.2v, ? sw = 300khz, l=21 0nh ( 0.2m ), hv cc= lvcc= 6.8v, c in =47uf x 4, c out =47 0 uf x3, 400lfm airflow, no heat sink, 25c ambient temperature , and 8 - layer pc b of 3.7 (l) x 2.6 (w). pwm controller loss and i nductor loss are not included. 3. v in =12v, v out =1.2v, ? sw = 400khz, l=15 0nh ( 0.2 9 m ), h vcc= lvcc= 7 v, c in =47uf x 4, c out =470uf x3, no airflow, no heat sink, 25c ambient temperature , and 8 - layer pc b of 3.7 (l) x 2.6 (w). pwm controller loss and i nductor loss are not included.
september 10 , 2012 | final datasheet 8 ir355 8 4 5 a integrated powirs tage ? timing diagram s fig ure 6 : IR3558 switching waveforms in 3.3v tri - state pwm mode figure 7 : IR3558 switching waveforms in international rectifiers active tri - level? (atl) pwm mode g a t e l p w m n o r m a l p w m a t l t r i - s t a t e a t l t r i - s t a t e n o r m a l p w m v a t l _ h i g h v a t l _ l o w v a t l _ t r i _ h i g h v a t l _ t r i _ l o w s w pwm sw gatel normal pwm tri - state tri - state v pwm _ high v pwm _ low v pwm _ tri normal pwm
september 10 , 2012 | final datasheet 9 ir355 8 4 5 a integrated powirs tage ? typical operating ch aracteristics circuit of figure 32 , v in =12v, v out =1.2v, ? sw = 400khz, l=150 nh ( 0.2 9 m ) , vcc= 5 v, hvcc =lvcc=7v, t amb = 25c , no heat sink, no air flow, 8 - layer pcb board of 3.7 ( l) x 2.6 ( w) , no pwm controller loss, no inductor loss, unless specified otherwise. f igure 8 : typical ir 3558 efficiency fig ure 9 : typical ir 3558 power loss figure 10 : safe operating area , t case < = 125c figure 11 : normalized power loss vs. input voltage figure 12 : normalized power loss vs. output voltage figure 13 : normalized power loss vs. switching frequency 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 0 5 10 15 20 25 30 35 40 output current (a) efficiency (%) 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 35 40 output current (a) power loss (w) 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 output voltage (v) normalized power loss -4.4 -3.3 -2.2 -1.1 0.0 1.1 2.2 3.3 4.4 5.5 6.6 7.7 8.8 case temperature adjustment (c) 0.85 0.90 0.95 1.00 1.05 1.10 1.15 5 6 7 8 9 10 11 12 13 14 15 input voltage (v) normalized power loss -3.3 -2.2 -1.1 0.0 1.1 2.2 3.3 case temperature adjustment (c) 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 200 300 400 500 600 700 800 900 1000 switching frequency (khz) normalized power loss -3.3 -2.2 -1.1 0.0 1.1 2.2 3.3 4.4 5.5 6.6 7.7 8.8 9.9 case temperature adjustment (c) 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 ambient temperature (c) output current (a) 400lfm 200lfm 100lfm 0lfm
september 10 , 2012 | final datasheet 10 ir355 8 4 5 a integrated powirs tage ? typical operating ch aracteristics (conti nued) circuit of figure 32 , v in =12v, v out =1.2v, ? sw = 400khz, l=150 nh ( 0.2 9 m ) , vcc= 5 v, hvcc=lvcc=7v, t amb = 25c , no heat sink, no air flow, 8 - layer pcb board of 3.7 (l) x 2.6 (w), no pwm controller loss, no inductor loss, unless specified otherwise. figure 14 : normalized power l oss vs. h vcc & lvcc voltage figure 15 : power loss vs. output inductor figure 16 : vcc current vs. switching frequency fig ure 17 : l vcc current vs. switching frequency figure 18 : h vcc current vs. switching frequency figure 1 9 : switching waveform in tri - state mode, i out = 0a pwm 5v/div sw 5v/div gatel 10v/div 400ns/div 0.0 0.5 1.0 1.5 2.0 2.5 3.0 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 fsw (khz) vcc current (ma) vcc=5.5v vcc=5v 0 5 10 15 20 25 30 35 40 45 50 55 60 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 fsw (khz) lvcc current (ma) lvcc=12v lvcc=7v lvcc=5v 0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 fsw (khz) lvcc current (ma) hvcc=12v hvcc=7v hvcc=5v 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 hvcc and lvcc voltage (v) normalized power loss -3.3 -2.2 -1.1 0.0 1.1 2.2 3.3 4.4 5.5 case temperature adjustment (c) 0.85 0.90 0.95 1.00 1.05 1.10 1.15 120 130 140 150 160 170 180 190 200 210 output inductor (nh) normalized power loss -3.3 -2.2 -1.1 0.0 1.1 2.2 3.3 case temperature adjustment (c)
september 10 , 2012 | final datasheet 11 ir355 8 4 5 a integrated powirs tage ? typical operating ch aracteristics (conti nued) circuit of figure 32 , v in =12v, v out =1.2v, ? sw = 400khz, l=150 nh ( 0.2 9 m ) , vcc= 5 v, hvcc=lvcc=7v, t amb = 25c , no heat sink, no air flow, 8 - layer pcb board of 3.7 (l) x 2.6 (w), no pwm controller loss, no inductor loss, unless specified otherwise. figure 20 : switching waveform in tri - state mode, i o ut = 40a figure 21 : pwm to sw delay s in tri - state mode, i out = 10a figure 2 2 : pwm tri - state delays in tri - state mode, i out = 10a figure 2 3 : pwm tri - state delays in tri - stat e mode, i out = 10a figure 2 4 : switching waveform in atl mode, i out = 0a figure 2 5 : switching waveform in atl mode, i out = 40a pwm 2v/div sw 5v/div gatel 10v/div 400ns/div pwm 2v/div sw 5v/div gatel 10v/div 400ns/div pwm 5v/div sw 5v/di v gatel 10v/div 400ns/div pwm 2v/div gatel 5v/div 100ns/div sw 5v/div pwm 2v/div gatel 5v/div 100ns/div sw 5v/div pwm 5v/div sw 5v/div 40ns/div gatel 5v/div
september 10 , 2012 | final datasheet 12 ir355 8 4 5 a integrated powirs tage ? typical operating ch aracteristics (conti nued) circuit of figure 32 , v in =12v, v out =1.2v, ? sw = 400khz, l=150 nh ( 0.2 9 m ), vcc= 5 v, hvcc=lvcc=7v, t amb = 25c , no heat sink, no air flow, 8 - layer pcb board of 3.7 (l) x 2.6 (w), no pwm controller loss, no inductor loss, unless specified otherwise. f igure 2 6 : pwm to sw delay s in atl mode , i out = 10a figure 2 7 : pwm tri - state delay s in atl mode , i out = 10a figure 2 8 : pwm tri - state delays in atl mode, i out = 0a figure 2 9 : en di sable delay , i out = 0a figure 30 : over temperature threshold vs. otset resistor figure 31 : switching waveform, i out = 40a, hvcc = lvcc = 12v en 5v/div gatel 5v/div 400ns/div sw 5v/div pwm 2v/div 40ns/div gatel 5v/div sw 5v/div pwm 2v/di v sw 5v/div 40ns/div gatel 5v/div pwm 2v/div sw 5v/div 40ns/div sw 5v/div pwm 2v/div sw 5v/div gatel 10v/div 400ns/div 30 40 50 60 70 80 90 100 110 120 130 140 150 1 10 100 1000 otset resistor (k) over temperature thresholds ( o c) high threshold low threshold
september 10 , 2012 | final datasheet 13 ir355 8 4 5 a integrated powirs tage ? theory of operation description the ir 3558 powirs tage ? is a synchronous buck driver with co - packed mosfets with integrated schottky diode , which provides system designers with ease of use and flexibility require d in cutting edge cpu, gpu and ddr m emory power delivery designs and other high - current low - profile applications . the ir 3558 is designed to work with a pwm controller . it accepts either regular 3.3v tri - state pwm signal or international rectifiers active tri - level (atl) pwm signal, which is selectable by mode pin. the ir 3558 provides enable input to control the converter output and reduce quiesecent current . the ir 3558 provides a over temperature f ault signal capable of detecting an over - temperature condition in the vicinity of the power stage. the over - temperature threshold is programmable from 70c to 150c. pwm mode selection the IR3558 features a mode pin which allows operation with two different pwm signal levels. grounding the mode pin allows the IR3558 to accept a regular tri - state pwm with si gnal from 0v to 3.3v for low to high transitions . a pwm voltage level in the tri - s tate window of 0.85v and 2.55v for 80ns hold off time results in turning off both the control and synchronous mosfets. floating mode pin or c onnecting it to vcc enables the IR3558 to accept irs proprietary atl mode , in which the pwm voltage level is from 0v to 1.8v for low to high transitions. a pwm voltage level greater than the tri - state high threshold (2.5v typical) turns off both the control and synchronous mosfets. regular 3.3v pwm mod e if mode pin is grounded, t he IR3558 a ccepts regular 3 - level 3.3v pwm input signals . as shown in figure 6, w hen pwm input is above v pwm_ high , the synchronous mosfet is turned off and the control mosfet is turned on. when pwm input is below v pwm _low , the control mosfet is turned off and synchronous mosfet is turned on. if pwm pin is floated , the built - in resistors pull the pwm pin into a tri - s tate region centered around 1.6 v. figures 19 - 23 show the pwm input and the corresponding sw and gatel output of the IR3558. active tri - level pwm mode when mode pin is floating, t he ir 3558 accepts a unique tri - level pwm control signal provided by an ir digital pwm controller . as shown in figure 7, the rising and falling edg es of the pwm signal transition between 0v and 1.8v to switch both the control and synchronous mosfets during norma l pwm operation . to turn both mosfets off simultaneously, the pwm signal crosses a tri - state voltage level higher th an the v atl_tri_high threshold (2.5v typical) . this threshold based tri - state results in a very fast disa ble with only a small propagation d elay. mosfet switching resumes when the pwm signal falls below the v atl_tri_low threshold ( 2.3v typical) into the normal pwm operating voltage range. figures 24 - 28 show the pwm input and the corresponding sw and gatel output of the IR3558. this fast tri - st ate operation eliminates the need for the pwm signal to dwell in the shutdown window , eliminating the delay time created by the pwm pull - up and pull - down resistors with the pwm trace routing capacitance. a de dicated body - braking? pin is not required , which simplifies the routing and layout . one advantage of the atl is the abi lity to quickly turn - off all synchronous mosfets during a load release event. this is known as body - braking? since all the load current is forced to flow momentarily through the body diodes of the mosfets , which discharges the inductor current faster and results in a much lower overshoot on the output voltage. the IR3558 provides a 1 ma typical pull - up current to drive the pwm input to the tri - state condition of 3.3v when the pwm contro ller output is in it s high impedance state. the 1 ma typical current is designed for driving worst case stray capacitances and transition the IR3558 into the tri - state condition rapidly to avoid a prolonged period of conduction of the control or synchronous mos fet during fault y conditions . once the pwm signal ha s been pulled up, the 1 ma current is disabled to reduce power consumption. enable control en is a 3.3v logic input. logic low disables pwm operation and places the power stage in tri - state , as shown in figure 29 . it also places the driver in a low power state with minimum quiescent current. logic high enables the device. integrated bootstrap diode the bootstrap circuit is used to establish the gate voltage for the high - side driver. it consists of a di ode and capacitor
september 10 , 2012 | final datasheet 14 ir355 8 4 5 a integrated powirs tage ? connected between the sw and boost pins of the device. the bootstrap capacitor stores the charge and provides the voltage requ ired to drive the internal control mosfet gate. the IR3558 features an integrated bootstrap diode to reduce ext ernal component count. this enables the IR3558 to be used effectively in cost and space sensitive designs. for ultra high efficiency designs, an exte rnal boot strap diode in parallel with the integrated bootstrap diode is recommended. a series resistor, 1 to 4, may be added to slow down the sw rising and limit the surge current into the boot strap capacitor on start - up . adjustable over temp erature threshold in a single phase regulator, over temperature of the power stage can happen due to the over current, inductor saturation or other faulty conditions. in a multiphase voltage regulator , d iffere nces in temperature from phase to phase can occur due to current unbalance, mis matched thermal solutions, airflow, surrounding components or manufacturing errors and can often cause poor efficiency or even system failures if not monitored . the IR3558 detects the die temperature of its internal mosfet d river . the otset feature allows the user to adjust the over temperature threshold from 70 c to 150 c using a simple re sistor between otset pin and ground . t he equation defini ng the over temperature threshold , t ots et as a function of r ots et is: leaving the ot set pin open will set the over temperature threshold at the default 150 c. figure 30 shows the values of r ot set chosen as a function of the desired over temperature threshold . the ot# flag is an open drain signal and is active low as the temperature of the IR3558 die exceeds the otset threshold . the ot# becomes high once the IR3558 temperature dro p s by the 20 c hysteresis. the ot# pin can be tied to a system level e nable to implement an over - temperature shutdown feature in a voltage regulator. t o monitor all the phases in a multiphase system, tie the ot# of all IR3558 together and connect it to sys tem enable. if ot# is not used it can be floated or connected to lgnd. adjustable hvcc and lvcc drive voltages hvcc and lvcc voltages can be independently adjusted to optimize high - side and low - side mosfet efficiency respectively. both voltage ranges are from 4.5v to 13.2v. higher hvcc and lvcc gate drive voltages improve efficiency at heavy load but lower efficiency at light load. higher hvcc voltage also causes undesirable higher switching node spike, as shown in figure 31. design procedures power loss calculation the single - phase ir 3558 efficiency and power loss measurement circuit is shown in figure 32 . figure 32 : ir 3558 power loss measurement the ir 3558 power loss is determined by, where both mosfet loss and the driver loss ar e included, but the pwm controller and the inductor losses are not included. figure 8 shows the measured single - ph ase ir 3558 efficiency under the default test conditions, v in =12v, v out =1.2v, ? sw = 400khz, l=150 nh ( 0.2 9 m ), pvcc (h vcc / lvcc) = 7 v, t ambient = 25c , no heat sink, and no air flow. the efficiency of an interleaved multiphase ir 3558 converter is always higher than that of a single - phase under the same conditions due to the reduced input rms current and more input/output capacitors. the measured single - phase ir 3558 p ower loss under the same co nditions is provided in figure 9 . otset otset r k k c c t ? ? ? ? ? ? ? ? 38 38 89 150 sw vin pgnd vcc boost otset hvcc lvcc mode en ir 3558 ot # v in v out c 2 47 uf x 4 c 5 0 . 22 uf c 4 0 . 22 uf r 2 2 . 49 k l 1 150 nh c 6 470 uf x 3 c 1 0 . 1 uf x 2 vcc r 1 10 k i vcc i in i out c 3 0 . 1 uf c 7 1 uf v sw cs + cs - lgnd pvcc i pvcc pwm out sw pvcc pvcc vcc cc in in loss i v i v i v i v p ? ? ? ? ? ? ? ?
september 10 , 2012 | final datasheet 15 ir355 8 4 5 a integrated powirs tage ? if any of the application condition, i.e. input voltage, output voltage, switching frequency, pvcc ( h vcc /lvcc ) mosfet driver voltage or inductance , is different from those o f figure 9 , a set of normalized power loss curves should be used . obtain the normalizing factors from figure s 11 - 15 for the new application conditions; multiply these factors by the power loss obtained from fig ure 9 for the required load current. as an exa mple, the power loss calculation procedures under different conditions, v in =10v, v out =1v, ? sw = 300khz, l=210 nh , pvcc ( h vcc / lvcc ) = 5v, i out =35 a, t ambient = 25c , no heat sink, and no air flow , are as follows. 1) determine the power loss at 35 a under the defa ult test conditions of v in =12 v, v out =1 .2 v, ? sw = 400khz, l=15 0 nh , pvcc (hvcc/lvcc) = 7 v, t ambient = 25c , no heat sink, and no air flow. it is 5.2 w from figure 9 . 2) determine the input voltage normalizing factor with v in =10v, which is 0.97 based on the dashe d lines in figure 11 . 3) determine the output voltage normalizing factor with v out =1v, which is 0.90 based on the dashed lines in figure 12 . 4) determine the switching frequency normalizing factor with ? sw = 300khz, which is 0.99 based on the dashed lines in fig ure 13 . 5) determine the mosfet drive voltage normalizing factor with pvcc ( hvcc / l vcc ) = 5v, which is 1.22 based on the dashed lines in figure 14 . 6) determine the inductance normalizing factor with l=210 nh , which is 0.96 based on the dashed lines in figure 15 . 7) multiply the power loss under the default conditions by the five normalizing factors to obtain the power loss under the new conditions , which is 5.2w x 0.97 x 0.90 x 0.99 x 1.22 x 0.9 6 = 5.3 w . safe operating area figure 10 shows the ir 3558 safe operating area with the case temperature controlled at or below 125c. the test conditions are v in =12v, v out =1.2v, ? sw =400khz, l=150 nh ( 0.2 9 m ), h vcc =lvcc = 7 v, t ambient = 0 c to 90 c , no heat sink, and a irflow = 0lfm / 100lfm / 200lfm / 400lfm. if any of the applicat ion condition, i.e. input voltage, output voltage, switching frequency, h vcc /lvcc mosfet driver volta ge, or inductance is different from those of figure 10 , a set of ir 3558 case temperature adjustment curves should be used. obtain the temperature deltas fr om figure s 11 - 15 for the new application conditions; sum these deltas and then subtract from the ir 3558 case temperature obtained from figure 10 for the required load current . the IR3558 safe operating area is obtained with the case temperature controlled at or below 125c. if a lower case temperature is desired, reduce the highest ambient temperature by the same delta. as an example, the highest ambient temperature calculation procedures for a different operating condition, v in =10v, v out =1v, ? sw = 300khz, l=210 nh , pvcc (h vcc /lvcc) = 5v, i out =35a, t ambient = 25c , no heat sink, and no air flow, are as follows. 8) from figure 10 , determine the highest ambient temperature at the required load current under the default conditions, which is 6 5 c at 35 a with 0lfm ai rflow and the ir 3558 case temperature of 125c. 9) determine the case temperature with v in =10v, which is - 0. 7 based on the dashed lines in figure 11 . 10) determine the case temperature with v out =1v, which is - 2.2 based on the dashed lines in figure 12 . 11) determi ne the case temperature with ? sw = 300khz , which is - 0. 2 based on the dashed lines in figure 13 . 12) determine the case temperature with pvcc ( hvcc / lvcc ) = 5v , which is +4.9 based on the dashed lines in figure 14 . 13) determine the case temperature with l=210nh , which is - 0.9 based on the dashed lines in figure 15 . 14) sum the ca se temperature adjustment from 9) to 13 ), - 0.7 - 2.2 - 0.2 +4.9 - 0.9 = +0.9 . deduct the delta from the highest ambient temperature in step 8 ) , 6 5 c - ( + 0.9 c) = 6 4 .1 c . 15) if the desire d IR3558 case temperature is 105c instead of 125c , subtract 20c ( =125c - 105c) from the highest ambient temperature obtained from 14), i.e. 64.1c - 20c = 44.1c.
september 10 , 2012 | final datasheet 16 ir355 8 4 5 a integrated powirs tage ? over temperature thr eshold set resistor r otset decide the desired over temperature th reshold, t ots et , based on the system requirement. leaving the ot set pin open will set the over temperature threshold at the 150 c. if the desired over temperature threshold is between 70c and 150 c, use the following equation to c alculate the otset resist or r ots et . figure 33 : over temperature threshold vs. orset resistor figur e 33 can also be used to determine the values of r otset . a 1% or better resistor should be used for the best accuracy. input capacitors c vi n at least two 10uf 1206 ceramic capacitors and one 0.1uf 0402 ceramic capacitor are recommended for decoupling the vin to pgnd connection . the 0.1uf 0402 capacitor should be on the same side of the pcb as the IR3558 and next to the vin and pgnd pins. adding additional capacitance and use of capacitors with lower esr and mounted with low inductance routing will improve efficiency and reduce overall system noise, especially in single - phase designs or during high current operation . bootstrap ca pacitor c b oo st a minimum of 0.22 uf 0402 capacitor is required for the b ootstrap circuit. a high temperature 0.22uf or greater value 0402 capacitor is recommended. it should be mounted on the same side of the pcb as the ir 3558 and as close as possible to th e b oost p in. a low inductance routing of the sw pin connection to the other terminal of the b ootstrap capacitor is strongly recommended. a series resistor, 1 to 4, may be added to slow down the sw rising and limit the surge current into the boot strap capacitor on start - up . vcc , hvcc and lvcc decoupling c apacitor s c vcc , c hvcc and c lv cc a 0.1uf ceramic decoupling capacitor is required at th e vcc pin. a 0.1uf to 1uf ceramic decoupli ng capacitor is required at the hvcc or lvcc pin. they should be mounted on the same side of the pcb as the ir 3558 . the vcc capacitor should be as close as possible to the vcc and lgnd . the hvcc and lvcc capacitors should be as close as possible to hvcc/lvcc and pgnd (pin 4 ) . low inductance routing for the decoupling capacitor s is strongly recommended. mounting of heat sin ks care should be taken in the mounting of heat sinks so as no t to short - circuit n earby compone nts. the vcc and b ootstrap capacitors are typically mounted on the same side of the pcb as the ir 3558 . the mounting height of these capacitors must be considered when selecting their package sizes. high output voltage design c onsiderations the ir 3558 is c apable of creating output voltages above the 3.3v recommended maximum output voltage as there are no restrictions inside the ir 3558 on the duty cycle applied to the pwm pin. however the output current rating of the device will be reduced as the duty cycle increases. in very high duty cycle applications sufficient time must be provided for replenishment of the bootstrap capacitor for the control mosfet drive . layout example contact international rectifier for a layout example suitable for your specific appli cation. ? ? ? ? ? ? ? ? k t c c k r otset otset 38 150 89 38 30 40 50 60 70 80 90 100 110 120 130 140 150 1 10 100 1000 otset resistor (k) over temperaturet threshold ( o c)
september 10 , 2012 | final datasheet 17 ir355 8 4 5 a integrated powirs tage ? metal and component placement ? lead land width should be equal to nominal part lead width. the minimum lead to lead spacing should be 0.2mm to prevent shorting. ? lead land length should be equa l to maximum part lead length +0.15 - 0.3 mm outboard extension and 0 to + 0.05mm inboard extension. the outboard extension ensures a large and visible toe fillet, and the inboard exten sion will accommodate any part misalignment and ensure a fillet. ? center pad land length and width should be equal to max imum part pad length and width. ? only 0.30mm diameter via shall be placed in the area of the power pad lands and connected to power p lanes to minimize the noise effect on the ic and to improve thermal performance . figure 34 : metal and component placement * contact i nternational r ectifier to receive an electronic pcb library file in cadence allegro or cad dxf/dwg format .
september 10 , 2012 | final datasheet 18 ir355 8 4 5 a integrated powirs tage ? solder resist ? the solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. the solder resist miss - alignment is a maximum of 0.05mm and it is recommended that the low power signal lead lands are all non solder mask defined (nsmd). therefore pulling the s/r 0.06mm will always e nsure nsmd pads. ? the minimum solder resist width is 0.13mm typical . ? at the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fille t so a solder resist width of 0.17mm remains. ? the dimensions of power land pad s, vin, pgnd, and sw, are non solder mask defined ( n smd ). the equivalent pcb layout becomes solder mask defined (smd ) after power shape routing. ? ensure that the solder resist i n - between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land . figure 35 : solder resist * contact i nternational r ectifier to re ceive an electronic pcb library file in cadence allegro or cad dxf/dwg format .
september 10 , 2012 | final datasheet 19 ir355 8 4 5 a integrated powirs tage ? stencil design ? the stencil apertures for the lead lands should be approximately 65% to 75 % of the area of the lead lands depending on stencil thickness . reducing the amount of s older deposited will minimize the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder rel ease. ? the low power signal stencil lead land apertures should therefore be shortened in length to keep area ratio of 65% to 75% while centered on lead land. ? the power pad s vin, pgnd and sw, land pad aperture s should be approximately 65% to 75 % area of so lder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open. solder paste on large pads is broken down into small sections with a minimum gap of 0.2mm between allowing for out - gassing during solder reflow. ? the maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste . figure 3 6 : stencil design * contact i nternational r ectifier to receive an electronic pcb library file in cadence allegro or cad dxf/dwg format .
september 10 , 2012 | final datasheet 20 ir355 8 4 5 a integrated powirs tage ? marking information figure 37 : pqfn 5 mm x 6mm package inf ormation figure 3 8 : pqfn 5 mm x 6mm 3558 m ? y w w ? xxxxx site / d ate / m arkin g c od e lot c od e
september 10 , 2012 | final datasheet 21 ir355 8 4 5 a integrated powirs tage ? data and specifications subject to change without notice. this product will be designed and qualified for the industrial market. qualification standards can be found on irs web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 - 7105 tac fax: (310) 252 - 7903 visit us at www.irf.com for sales contact information . www.irf.com

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